1. Field of the Invention
The present invention relates in general to the manufacture of semiconductor integrated circuits (IC), and more particularly to a method of fabricating contacts of semiconductor devices in a self-aligned manner by using a liquid-phase oxide-deposition (LPD) process.
2. Description of the Prior Art
A self-aligned contact process is an ordinary method used in the fabrication of semiconductor devices. FIGS. 1a to 1e show, in cross-sectional view, the process steps of a prior art self-aligned contact process. First, referring to FIG. 1a, first oxide layer 12, first polysilicon layer 11, and second oxide layer 13 are formed on semiconductor substrate 1 successively. First polysilicon layer 11 can be implanted with impurities to improve its conductivity. Next, second oxide layer 13, first polysilicon layer 11, and first oxide layer 12 are patterned by lithography and etching processes to form gate electrode 18 and expose area 16 of the semiconductor substrate 1 for source/drain regions. Using gate electrode 18 as a mask, an impurity is implanted into area 16 to form lightly doped source/drain regions 32. Third oxide layer 14 is then deposited on the surfaces of gate electrode 18 and lightly doped source/drain regions 16.
Referring to FIG. 1b, third oxide layer 14 is anisotropically etched, preferably by reactive ion etching (RIE), to leave first sidewall spacer 27 on the sidewalls of gate electrode 18. Similarly, an impurity is then implanted into area 16 to form heavily doped source/drain regions 31 using the gate electrode 18 and the first sidewall spacer 27 as a mask. Fourth oxide layer 35 is deposited on the surfaces of gate electrode 18, first sidewall spacer 27, and heavily doped source/drain regions 31.
Referring to FIG. 1c, layer of photoresist 45 is coated and patterned by a lithography process. Fourth oxide layer 35 is then anisotropically etched preferably by RIE to expose a portion of heavily doped source/drain regions 31, namely contact 29. To ensure that no residue of fourth oxide layer 35 is left on contact 29, an over-etching is usually used at this stage. This will lead to the formation of over-etched area 37 in second oxide layer 13, which may likely cause an electrical short circuit. In addition, second sidewall spacer 28 is also formed on the sidewalls of first sidewall spacers 27 due to the fact that fourth oxide layer 35 is etched anisotropically.
Referring to FIG. 1d, photoresist 45 is removed by an appropriate solvent. Second polysilicon layer 46 is then deposited on the exposed surfaces of the substrate. Second polysilicon layer 46 is connected to heavily doped source/drain regions 31 through the contact 29 in a self-aligned manner. Finally, as can be seen in FIG. 1e, second polysilicon layer 46 is patterned by a lithography and etching processes to form interlevel conductive layer 42.
The prior art self-aligned contact process, however, has two drawbacks. First, gate electrode 18 is likely to short to contact 29 since second oxide layer 13 over gate electrode 18 (i.e. over-etched area 37) is easily etched away while anisotropically etching fourth oxide layer 35. Second, the area of contact 29 is reduced due to the formation of second sidewall spacer 28 on the sidewalls of first sidewall spacer 27. Therefore, a need has arisen for a simple and more reliable process to form a self-aligned contact of a semiconductor device which overcomes the drawbacks of the prior art process.